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Inter-Integrated Circuit
9.4
Functional description
This section provides a complete functional description of the I 2 C module.
9.4.1
I 2 C protocol
The I 2 C bus system uses a Serial Data Line (SDA) and a Serial Clock Line (SCL) for data transfer. All
devices connected to it must have open drain or open collector outputs. A logic AND function is exercised
on both lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
? START signal
? Slave address transmission
? Data transfer
? STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The I 2 C bus system
communication is described briefly in the following sections and is illustrated in Figure 9-9 .
MSB
LSB
MSB
LSB
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6 D5
D4
D3
D2 D1
D0
Start
Signal
MSB
Calling Address
READ/ ACK
WRITE Bit
LSB
MSB
Data Byte
LSB
No Stop
ACK Signal
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
READ/ ACK Repeated
WRITE Bit Start
Signal
New Calling Address
READ/ No Stop
WRITE ACK Signal
Bit
Figure 9-9. I 2 C bus transmission signals
9.4.1.1
START signal
When the bus is free that is, no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in Figure 9-9 , a START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
168
Freescale Semiconductor, Inc.
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